Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation
نویسندگان
چکیده
منابع مشابه
Exploiting symmetry when verifying transistor - levelcircuits by symbolic trajectory
|We describe the use of symmetry for veriication of transistor-level circuits by Symbolic Trajectory Evaluation (STE). We present a new formulation of STE which allows a succint description of symmetry properties in circuits. Symmetries in circuits are classiied as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from similarities in the handling o...
متن کاملExploiting Symmetry When Verifying Transistor-level Circuits by Symbolic Trajectory Evaluation
In this paper we describe the use of symmetry for verii-cation of transistor-level circuits by symbolic trajectory evaluation. We show that exploiting symmetry can allow one to verify systems several orders of magnitude larger than otherwise possible. We classify symmetries in circuits as structural symmetries, arising from similarities in circuit structure, data symmetries, arising from simila...
متن کاملFormal Veri cation of Memory Arrays
Veri cation of memory arrays is an important part of processor veri cation. Memory arrays include circuits such as on-chip caches, cache tags, register les, and branch prediction bu ers having memory cores embedded within complex logic. Such arrays cover large areas of the chip and are critical to the functionality and performance of the system. Hence, these circuits are custom designed at the ...
متن کاملFormal Veriication by Symbolic Evaluation of Partially-ordered Trajectories
Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modiied form of symbolic simulation. The desired system properties are expressed in a notation combining Boolean expressions and the temporal logic \next-time" operator. In its simplest form, each property is expressed as an assertion A =) C], where the antecedent A expresses some assumed c...
متن کاملFormal Veri cation by Symbolic Evaluation of Partially - OrderedTrajectories
Symbolic trajectory evaluation provides a means to formally verify properties of a sequential system by a modiied form of symbolic simulation. The desired system properties are expressed in a notation combining Boolean expressions and the temporal logic \next-time" operator. In its simplest form, each property is expressed as an assertion A =) C], where the antecedent A expresses some assumed c...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1997